This invention relates to a semiconductor device having a wiring pattern wherein two wiring are electrically connected with each other through a contact hole and also to a method for manufacturing the same.
Contact holes, which allow two wirings formed in different layers (upper and lower layers) to be electrically connected therethrough, are determined in number depending on the width of wirings layers to be connected therethrough and the current passing through the contact holes. It is the usual practice that plural contact holes are provided for one wiring when a relatively wide wiring layer called “wide wiring” is selected for the connection. In this connection, however, where two wirings having significantly large wiring widths are connected, e.g. when a wide wiring and a fine wiring having a smaller wiring width are connected with each other (for instance, in case of leading out from a power supply line by means of a fine wiring for fixing a potential), it is necessary to determine the number of contact holes in accord with the width of the fine wiring, so that the wide wiring may be unavoidably connected through a single contact hole.
On the other hand, in order to cope with the wiring delay caused by the scale down of wiring pitches, wiring materials for forming a wiring layer or insulating materials used for insulation between wiring layers have now given way to the use of low resistance wiring materials typical of which is Cu (copper) and low dielectric materials typical of which are SiLK, SiOC, and, the like. Cu for use as a low resistance wiring material has been reported as being more excellent in electromigration resistance than Al that has hitherto been in wide use as a wiring material. Nevertheless, where a fine wiring is formed by use of Cu, there has never been known an appropriate etching gas for permitting a Cu to be etched at a high selection ratio relative to an underlying insulating film in a dry etching procedure and thus, it is usual to form a buried wiring according to the Damascene technique. Especially, the dual Damascene technique wherein a contact hole or holes formed in an insulating film and a wiring groove, at which a buried wiring is formed, are simultaneously filled is promising from the standpoint of enlargement of an alignment margin by lithography and the reduction in number of steps. The forming method of a buried wiring using Cu is described, for example, in Japanese Patent Laid-open No. Hei 10-154709.
However, the use of Cu as a wiring material has the following disadvantages. As shown in FIGS. 19A and 19B, when a semiconductor device of a type having a wiring pattern wherein a lower wide wiring 401 and an upper fine wiring 402 are electrically connected through a contact hole 403 was subjected to a high temperature standing test for evaluating the reliability of the wirings, it was confirmed that the wiring resistance rose, resulting in the phenomenon where electric connection was interrupted. The analysis of defectives resulting from the phenomenon reveals that a portion 404 of Cu disappears or becomes voided at the wide wiring 401 side below the contact hole 403. In this instance, the wide wiring 401 is formed below the contact hole 403, and a similar phenomenon has been confirmed in the case where the wide wiring is formed over the contact hole. More particularly, as shown in FIGS. 20A and 20B, where a semiconductor device having a wiring pattern wherein an upper wide wiring 501 and a low fine wiring 502 are electrically connected through a contact hole 503 was subjected to a high temperature standing test for evaluating the reliability of the wirings, it was confirmed that a voided portion 504 of Cu was found at the inside of the contact hole 503.
Such voiding of Cu is liable to occur when the dimensional relationship between the wiring width of the wide wiring and the diameter of the contact hole satisfies a given range of conditions, especially, in case where the wide wiring and the fine wiring are electrically connected with each other through one contact hole. According to the experiment made by the present inventor, the voiding of Cu was observed when the width of a wiring was at 1.0 μm and the diameter of contact hole connecting thereto was at 0.14 μm. In order to avoid the voiding of Cu, it is effective to set the dimensional relationship between the wide wiring and the contact hole so as not to satisfy such conditions as mentioned above. It should be noted that because many limitation conditions have to be cleared up upon designing a wiring pattern, it is very difficult to optimize the dimensional relationship between the wide wiring and the contact hole while priority is given to the avoidance of the voiding of Cu.
Although how Cu becomes voided is not clear at present, the voiding mechanism is considered as follows: as reported, for example, in “Stress-induced Voiding Under Vias Connected to Wide Cu Metal Leads” (p. 312–321) of “IRPS (International Reliability Physics Symposium) 2002”, the voiding of Cu resulting from stress migration, i.e. voids caused by the grain growth in a Cu film, is concentrated at a portion, which is relatively low in bonding (i.e. a portion where stress is released) by the influence of the stress caused by the difference in coefficient of thermal expansion between the wiring film and the insulating film and the stress of the insulating film per se, thereby causing Cu to be voided.